Output:
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Starting new simulation on Di. 16. Jun 2015 at 23:42:07:961

creating netlist... done.
Starting /home/guilherme/local/qucs/devel-debug/bin/qucsator

project location: 
modules to load: 0
factorycreate.size() is 0
factorycreate has registered:
parsing netlist...
checking netlist...
subcircuit root
  R:RD _net0 _net1 R="0.2" Temp="26.85" Tc1="0" Tc2="0" Tnom="26.85"
  Vdc:VDC _net2 gnd U="13.5V"
  Vdc:VGEN _net3 _net2 U="200V"
  C:CS _net2 _net4 C="4e-08F"
  R:RE _net2 _net0 R="0.4" Temp="26.85" Tc1="0" Tc2="0" Tnom="26.85"
  C:CL _net2 _net1 C="4e-08F"
  TR:TR1 Type="lin" Start="0" Stop="2e-07" Points="401" IntegrationMethod="Trapezoidal" Order="2" InitialStep="1e-09s" MinStep="1e-16" MaxIter="150" reltol="0.001" abstol="1e-12A" vntol="1e-06V" Temp="26.85" LTEreltol="0.001" LTEabstol="1e-06" LTEfactor="1" Solver="CroutLU" relaxTSR="no" initialDC="yes" MaxStep="0"
  R:RI _net1 Puls3b R="50" Temp="26.85" Tc1="0" Tc2="0" Tnom="26.85"
  Switch:S2 _net4 _net0 init="off" time="1e-08s" Ron="0" Roff="1e+09" Temp="26.85" MaxDuration="1e-06" Transition="spline"
  Switch:S1 _net3 _net4 init="on" time="9e-09s" Ron="0" Roff="1e+09" Temp="26.85" MaxDuration="1e-06" Transition="spline"
netlist content
      2 Switch instances
      2 C instances
      3 R instances
      2 Vdc instances
      1 TR instances
creating netlist...
NOTIFY: TR1: creating node list for initial DC analysis
NOTIFY: TR1: solving initial DC netlist
NOTIFY: TR1: creating node list for transient analysis
NOTIFY: TR1: solving transient netlist





















Simulation ended on Di. 16. Jun 2015 at 23:42:08:356
Ready.



Errors:
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